Coral NPU Completes Its 32-bit Design: Matrix Engine, IREE Compiler v1.0 and What to Check Before You Target It

Google Research says the 32-bit Coral NPU architecture is now complete, and that an open compiler and two developer boards are available. If you build on-device ML, the useful part is the toolchain claim: one model path from JAX, PyTorch or TensorFlow to several chips. The numbers are Google's, and I have not run any of this.

This article summarizes the October 20 post, Unifying Edge AI: How Coral NPU's open standard brings portable, energy-viable intelligence from model to silicon. I read the post text. I did not open the GitHub repositories, datasheets or board pages, so product details below are as the post states them.

What Google says was released

The post lists these milestones:

• The full 32-bit architecture. Earlier milestones covered a C-programmable RISC-V scalar frontend, an RVV v1.0 vector co-processor, and a memory subsystem with floating point. Milestone 4, the Matrix Execution Unit, completes it.
• Coral Compiler v1.0, built on IREE/MLIR. It takes JAX, PyTorch and TensorFlow models through StableHLO and TOSA to the Coral NPU target.
• New chips and boards. Synaptics Astra SR200 series (400 GOPS, MCU class), a new Coralboard SR dev kit, and general availability of the Coralboard SL (1 TOPS) through DigiKey.
• Complete 32-bit RTL on GitHub, according to the post.

The matrix engine

Per the post, the Matrix Execution Unit follows the RISC-V VME specification and uses an outer-product multiply-accumulate engine that does 256 MACs per cycle. Google's argument is that vector engines waste energy moving weights and activations for matrix math, and an outer-product design reuses them in local registers. It says the unit is configurable up to 1 TOPS and targets 10 mW average power for inference.

Read the 10 mW figure as a target, which is the post's own word. It is not a measured result for a shipping part, and the post does not say under which workload it applies.

The compiler claim

The compiler partitions work between the host CPU and the Coral NPU core, fuses operators, tiles matrices to fit local SRAM and accumulators, and lowers to scalar, vector and matrix instructions. Google also points to the MPACT simulator and a reference FPGA design so teams can benchmark before silicon exists.

The stated promise is "optimize a model once and deploy it" across vendors and power levels. That is the claim worth testing. Compilers for edge accelerators often differ in which operators fall back to the CPU, and the post itself names this fallback problem as the cost of the fragmented edge.

Hardware partners

The post says Synaptics launches the SR200 series on October 20, with second-generation Coral NPU IP including the Milestone 2 vector core, aimed at wearables and industrial sensors. It says Coralboard SL is built on the Astra SL2619 with a 1 TOPS subsystem. It names VeriSilicon for design implementation and verification, and GlobalFoundries on its 12LP+ process, with figures such as 70% faster core timing and up to 15% smaller standard-cell area across RTL iterations. I take those as Google's reported numbers.

Note that the SR200 uses the Milestone 2 design (vector), not the new matrix unit, per the post. The 1 TOPS matrix configuration is a design option for silicon teams.

What I would check before targeting it

These are my untested suggestions.

1. Operator coverage. Compile your actual model and see which operators land on the NPU and which fall back to the CPU. The compiler's partition output should show this.

2. Quantization path. Check how the toolchain expects you to quantize, and whether your accuracy holds.

3. Simulator versus board. Use MPACT for early checks, then confirm latency and power on a real Coralboard rather than trusting target numbers.

4. Which board matches the claim. The 10 mW and 1 TOPS targets belong to different configurations. Pick the board by the workload you need.

5. Model size. The post mentions compact transformers like Gemma as a possible workload. Verify memory fit on the specific board.

6. License and RTL terms, if you are on a silicon team. I did not read them.

What I would not conclude

• That sub-10 mW multimodal inference is available today. It is a design target.
• That "optimize once, run everywhere" works for your model. That is the claim to test.
• That the roadmap items (64-bit architecture, CHERI security support) have dates. The post says only that work is under way.

Frequently asked questions

What is Coral NPU?

An open RISC-V based neural processing unit design from Google Research, with an open compiler toolchain, per the post.

What is new on October 20?

The completed 32-bit architecture including the Matrix Execution Unit, Coral Compiler v1.0, the Synaptics SR200 chips, the Coralboard SR, and GA of the Coralboard SL.

What frameworks does the compiler accept?

JAX, PyTorch and TensorFlow, through StableHLO and TOSA, according to the post.

How fast is it?

Google says up to 1 TOPS for the matrix unit configuration, 400 GOPS for the SR200 and 1 TOPS for the Coralboard SL. These are vendor figures.

How much power does it use?

Google targets 10 mW average power for inference on the matrix-unit design. It is a target.

Where can I buy a board?

The post says the Coralboard SL is available through DigiKey. I did not check stock or price.

What comes next?

The post mentions a 64-bit Coral NPU architecture and CHERI support, without dates.

Sources

• Google Developers Blog, Unifying Edge AI: How Coral NPU's open standard brings portable, energy-viable intelligence from model to silicon (October 20, 2026). All claims above. Post text read; linked repos and datasheets not opened.